The brief
The client needed a small, receive-only unit that listens on a narrowband UHF allocation and raises a local alert when a burst is present, with a coarse close / medium / far strength band. No decoding: just reliable detection, a simple interface, and USB-C power.
Revision 1: prove it with off-the-shelf tuners
The first revision turned the client’s software prototype into hardware: a Raspberry Pi Compute Module 5 carrier with four shielded tuner channels behind a shared LNA and a four-way splitter, a USB hub and USB-C power delivery, on a 6-layer board. It was built and brought up, including debugging a suspected power short that turned out to be a body-diode reading, and an RF chain measurement that isolated a gain-stage fault.
Revision 2: one transceiver instead of four tuners
R2 replaced the four narrowband tuners with a single AD9361 RF transceiver and a Zynq-7010 system-on-module, turning four hardware channels into digital channelization:
- RF front end: ESD protection, a band-pass filter, a low-noise amplifier and a 30 dB attenuator ahead of a balun into the transceiver. The LNA and filter chain was simulated in QUCS with the vendors’ own S-parameter models before layout.
- Data path: LVDS from the transceiver to the SoC, routed as length-matched pairs on an inner layer.
- Power: sequenced rails from USB-C, with isolated analog supplies for the transceiver.
- Firmware specification: detection, strength banding and alert behavior, written as a spec for the firmware developer.
I owned the architecture, full schematic, simulation and design reviews. The production layout was done by a partner layout house under my direction and review, with a 6-layer stackup and ±10% impedance control.
What the pre-fab review caught
A structured schematic and datasheet review before release found issues that would have cost a board spin:
- Two status LEDs that could never light: their forward voltage exceeded the 1.8 V I/O bank driving them.
- LVDS standards versus bank voltage: on this SoC’s I/O banks, LVDS outputs need a 2.5 V supply, so the clock-return path and bank voltages were flagged for correction.
- The firmware spec and the hardware disagreed on which indicators were GPIO-driven, which was caught before the firmware work started.
That’s the value of a review gate: problems like these are cheap to fix in a schematic and expensive to fix on a board.